This invention relates to semiconductor device and its manufacturing method, particularly to a wiring formed inside semiconductor device and its manufacturing method.
The metalization technique to form wiring plays a very important role in manufacturing semiconductor integrated circuits. Particularly with recent high-density integration of device component parts, the wiring line width is also being shifted from the micron order to the submicron order. In addition, wiring lines are deposited with two, three or more layers to increase the degree of freedom in pattern design.
Conventional semiconductor devices and their manufacturing method are described by the sectional drawings of FIG. 1.
First of all, as shown in FIG. 1(a), an n.sup.+ -type diffusion layer 2 is formed in the specified position on the surface of a p-type semiconductor substrate 1 before a silicon oxide layer 3 is deposited on the entire surface by the CVD method. A BPSG layer 4 is also deposited on the entire surface of this silicon oxide layer 3.
Contact holes 5 are then formed on the n-type diffusion layer 2 by a lithographic technique and a reactive ion etching technique (RIE).
Next, as shown in FIG. 1(b), aluminum is deposited on the entire surface by sputtering before patterning is made according to the first wiring pattern by the lithographic technique and the first aluminum wiring 21 is formed.
As shown in FIG. 1(c), a silicon oxide layer 22 is deposited on the entire surface by a plasmatic CVD method, and then the surface is planarized, for example, by etch-back, and further through holes 23 are formed to connect with the first aluminum wiring 21.
Further, as shown in FIG. 1(d), aluminum is deposited on the entire surface, patterning is made according to the second wiring pattern and the second aluminum wiring 26 is formed. Finally, the whole surface is coated with a PSG passivation layer 27.
However, the semiconductor devices manufactured by the above-mentioned conventional method have had the following problems.
In the conventional method, the wiring material of aluminum is deposited by sputtering. Therefore, the sputtering of aluminum atoms is in one direction and only a little aluminum is deposited on the side walls of concaves like contact holes 5, sometimes in such a very small thickness as ten percent of the aluminum layer thickness of the flat part. Furthermore, this may cause a gap 28 as shown in FIG. 1(d). Phenomena like this become notable with an increased ratio (aspect ratio) of the sum of the thickness of the BPSG layer 4 and silicon oxide layer 3 to diameter D of contact hole 5 because of microminiaturization of component parts. The aspect ratio also increases with microminiaturization in the case of through holes. When the layer thickness of the first aluminum wiring 5 on the side wall of contact hole 5 becomes thinner, electromigration and/or stressmigration occur, resulting in lower reliability of the wiring.
Furthermore, the aluminum wiring has to be microminiaturized for higher integration of the semiconductor device. However, it was very difficult to form finer wiring patterns by conventional manufacturing methods. Even if finer resist patterns could be achieved with advanced lithographic techniques, accurate etching using the resist patterns becomes impossible. The reason for this is that the bottom area of the resist patterns is removed at the time of etching because the sectional shape of the resist pattern is trapezoidal and the side of aluminum is etched to a narrower pattern width.
Furthermore, in the photo-engraving process (PEP) using the photographic etching technique, irradiation of electromagnetic waves unnecessary for wiring resist patterns occurs because of reflection from wiring material, etc. at level differences caused by unevenness under the resist film during the exposure to electromagnetic waves, such as g-ray (436 nm) or ultraviolet rays after lamination of the resist film. Consequently, when the resist is of positive type, lack of the developed resist patterns occurs in the part exposed to unnecessary electromagnetic waves. Therefore, if the wiring material is etched using a resist pattern as a mask, the wiring becomes vermiculated. When the resist is of the negative type, an unexpected wiring pattern is formed in the area of the exposed wiring pattern exposed to unnecessary electromagnetic waves. This condition leads to a defect and lower reliability of the wiring, so it can be understood that the inferiority of planarity caused by an increased degree of integration is a problem.
Furthermore, generally speaking, silicon oxide layer 22 or 27 is deposited as an interleveldielectric film after the aluminum wiring is formed. By conventional deposition methods, the shape of deposition becomes overhung as a silicon oxide layer 22 shown in FIGS. 2(a) and (b). For this reason, depositing over a certain thickness forms cavities 24 on the space of aluminum wiring 21 and/or contact holes 5 as shown in FIGS. 1(c), (d), 2(a) and (b).
In conventional cases, as mentioned above, the decrease of thickness of the aluminum circuit layer on the side wall of contact holes, difficulty of micropattern formation, vermiculation of the wiring caused by reflection on level differences, formation of a unexpected wiring pattern and the existence of cavities in the silicon oxide layer have caused lower reliability of semiconductor devices. These problems have become more important with the microminiaturization and complexity of recent semiconductor devices.